Enhancing the Memory Performance of Embedded Systems with the Flexible Sequential and Random Access Memory

The on-chip memory performance of embedded systems directly affects the system designers’ decision about how to allocate expensive silicon area. We investigate a novel random access memory (RAM) architecture for embedded systems that allows both random-access and sequential-access for reads and writes. To realize sequential accesses, small “links” are added to each row in the RAM array to point to the next row to be prefetched. The potential cache pollution caused by prefetching is ameliorated by a small cache structure called a sequential access buffer (SAB). To evaluate the architecture-level performance of the flexible sequential and random access memory (FSRAM), we run the Mediabench benchmark programs [1] on a modified version of the Simplescalar simulator [2]. Our results show that the FSRAM improves the performance of a baseline processor with a 16KB data cache up to 55% on the benchmark programs tested, with an average improvement of about 9%. We also designed RTL and SPICE models of the FSRAM to evaluate its potential cost and delay characteristics [3]. Our design shows that the FSRAM significantly improves memory access time, while reducing power consumption, with negligible area overhead.